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1 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product general description general description general description general description general description em73361a is an advanced single chip cmos 4-bit micro-controller. it contains 3k-byte rom, 52-nibble ram, 4-bit alu, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. em73361a also contains 3 interrupt sources, 1 input port, 4 bidirection i/o ports, built-in watch-dog-timer counter, tone generator and lcd driver (27x3 to 13x3). except low-power consumption and high speed, em73361a also have a sleep mode operation for power saving. features features features features features ? operation voltage : 2.2v to 3.6v(clock frequency : 32k hz). clock source : single clock system for crystal, connect a external resistor or external clock source available by mask option. instruction set : 109 powerful instructions. instruction cycle time : 122s for 32k hz. rom capacity : 3072 x 8 bits. ram capacity : 52 x 4 bits. input port : 1 port (p0)(pull-up and pull-down resistor with wakeup function available by mask option). bidirection port : 4 ports (p4, p5, p6, p7) are available by mask option. (each i/o pin is push-pull and open-drain available by mask option) p4.0 is high current pin (p4.0 and tone available by mask option). p4.2~p4.3, p5, p6 and p7 are shared with seg26-seg13 by mask option. 12-bit timer/counter : two 12-bit timer/counters are programmable for timer mode. low voltage reset (lvr) : reset at 1.5v, and reset release at 1.8v. tone generator : there is a built-in tone generator. built-in time base counter : 22 stages. subroutine nesting : up to 13 levels. interrupt : external . . . . . 2 external interrupt (int0, int1). internal . . . . . . 2 timer overflow interrupts. 1 time base interrupt. lcd driver : 27 x 3 to 13 x 3 dots available by mask option. capacitor divider and resistor divider are available by mask option.1/3, 1/2 and static three kinds of duty (1/2 bias) selectable. the programming method of lcd driver is i/o mapping. built-in watch-dog-timer : the wdt is enabled or disabled by mask option. power saving function : sleep mode and hold mode. package type : em73361aah chip form 46 pins. EM73361AAQ qfp 100 pins. applications applications applications applications applications em73361a is suitable for application in family appliance, consumer products, hand held games and the toy controller.
2 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product pin configurations pin configurations pin configurations pin configurations pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 nc nc nc nc p7.1/seg15 p7.2/seg14 p7.3/seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 nc nc nc nc nc nc nc nc nc nc nc seg2 seg1 seg0 com1 com0 vee vb va xin xout nc nc nc nc nc nc nc nc nc nc nc nc nc nc p4.1/wdt p4.0/tone tone p0.3/wakeup3 p0.2(int0)/wakeup2 p0.1/wakeup1 p0.0(int1)/wakeup0 reset nc nc nc nc nc nc nc nc nc nc test nc nc nc nc nc nc nc nc nc nc EM73361AAQ qfp 100 nc nc nc nc vdd vss p4.3/seg25 p4.2/seg26 com2 p5.0/seg24 p5.2/seg22 p5.1/seg23 p6.0/seg20 p5.3/seg21 p6.2/seg18 p6.1/seg19 p7.0/seg16 p6.3/seg17 nc
3 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product symbol symbol symbol symbol symbol pin-type pin-type pin-type pin-type pin-type function function function function function v dd power supply (+) v ss power supply (-) reset reset-a system reset input signal, low active mask option : none pull-up xin osc-a/osc-f crystal/external resistor or external clock source connecting pin xout osc-a/osc-f crystal/external resistor connecting pin p0.0(int1)/wakeup0, input-j 2-bit input port with external interrupt sources input and sleep/hold p0.2(int0)/wakeup2 releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, none wakeup disable, pull-down p0.1/wakeup1, input-h 2-bit input port with sleep/hold releasing function p0.3/wakeup3 mask option : wakeup enable, pull-up wakeup enable, none pin descriptions pin descriptions pin descriptions pin descriptions pin descriptions function block diagram function block diagram function block diagram function block diagram function block diagram interrupt control time base 12-bit timer counter (ta,tb) system control instruction decoder instruction register rom pc data bus reset control frequency doubler timing generator sleep mode control data pointer acc alu flag zc s g stack pointer stack ram hr lr i/o control p0.0(int1)/wakeup0 p0.1/wakeup1 p0.2(int0)/wakeup2 p0.3/wakeup3 reset clock generator xin xout lcd driver tone generator wdt va vb vee com0~com2 seg0~seg12 p4.0/tone p4.1/wdt tone p4,p5,p6,p7/seg(26..13)
4 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product function descriptions function descriptions function descriptions function descriptions function descriptions program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) 3 k x 8 bits program rom contains user's program and some fixed data . the basic structure of program rom can be divided into 4 parts. 1. address 000h: reset start address. 2. address 002h - 00ch: 4 kinds of interrupt service routine entry addresses . 3. address 00eh-086h : scall subroutine entry address, only available at 00eh,016h,01eh,026h, 02eh, 036h, 03eh, 046h, 04eh, 056h, 05eh, 066h, 06eh, 076h ,07eh, 086h . 4. address 000h - 7ffh : lcall subroutine entry address 5. address 000h - bffh : except used as above function, the other region can be used as user's program region. address 3072 x 8 bits 000h reset start address 002h int0 ; external interrupt service toutine entry address 004h 006h trga; timer/counter a interrupt service routine entry address 008h trgb; timer/counter b interrupt service routine entry address 00ah tbi; time base interrupt service routine entry address 00ch int1; external interrupt service routine entry address 00eh 086h bffh symbol symbol symbol symbol symbol pin-type pin-type pin-type pin-type pin-type function function function function function wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p4.0/tone i/o-o 1-bit bidirection i/o pin or inverse tone generator output mask option : tone enable, push-pull, high current pmos tone disable, open-drain tone disable, push-pull, high current pmos tone disable, push-pull, low current pmos p4.1/wdt i/o-d 1-bit bidirection i/o pin with watch-dog-timer output mask option : open-drain push-pull p4(2..3)/seg(26..25) i/o-p 4-bit bidirection i/o ports are shared with lcd segment pins p5(0..3)/seg(24..21) mask option : segment enable, open-drain p6(0..3)/seg(20..17) segment disable, push-pull p7(0..3)/seg(16..13) segment disable, open-drain tone built-in tone generator output va, vb, vee connect the capacitors for lcd bias voltage com0~com2 lcd common output pins seg0~seg12 lcd segment output pins test tie vss as package type, no connecting as cob type scall, subroutine call entry address . . .
5 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product stack: there are 13 - level (maximum) stack for user using for subroutine (including interrupt and call). user can assign any level be the starting stack by giving the level number to stack pointer (sp). zero- page: from 00h to 0fh is the location of zero-page. it is used as the pointer in zero -page addressing mode for the instruction of "std #k,y; add #k,y; clr y,b; cmp k,y". program example: to wirte immediate data "07h" to address "03h" of ram and to clear bit 2 of ram. std #07h, 03h ; ram[03] 07h clr 0eh,2 ; ram[0eh] 2 0 increment address 20h - 2fh 30h - 33h level 0 level 4 level 8 level 12 level 1 level 5 level 9 level 2 level 6 level 10 level 3 level 7 level 11 increment 00h - 0fh 10h - 1fh stack zero-page data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) there is total 52 - nibble data ram from address 00 to 33h data ram includes 3 parts: zero page region, stacks and data area. ldax ldax ldax ldax ldax acc acc acc acc acc rom[dp] rom[dp] rom[dp] rom[dp] rom[dp] l l l l l ldaxi ldaxi ldaxi ldaxi ldaxi acc acc acc acc acc rom[dp] rom[dp] rom[dp] rom[dp] rom[dp] h h h h h ,dp+1 ,dp+1 ,dp+1 ,dp+1 ,dp+1 dp is a 12-bit data register which can store the program rom address to be the pointer for the rom code data. first, user load rom address into dp by instruction "stadpl, stadpm, stadph", then user can get the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi". program example: read out the rom code of address 777h by table-look-up instruction. ldia #07h; stadpl ; [dp] l 07h stadpm ; [dp] m 07h stadph ; [dp] h 07h, load dp=777h : ldl #00h; ldh #03h; ldax ; acc 6h stami ; ram[30] 6h ldaxi ; acc 5h stam ; ram[31] 5h ; org 777h data 56h; : table-look-up instruction is depended on the data pointer ( dp ) to indicate to rom address, then to get the rom code data. user's program and fixed data are stored in the program rom. user's program is according the pc value to send next executed instruction code. fixed data can be read out by table-look-up instruction.
6 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product when user using any instruction of call or subroutine, before entry the subroutine, the previous pc address will be saved into stack until return from those subroutines, the pc value will be restored by the data saved in stack. data area: except the special area used by user, the whole ram can be used as data area for storing and loading general data. addressing mode (1) indirect addressing mode: indirect addressing mode indicates the ram address by specified hl register. for example: ldam ; acc ram[hl] stam ; ram[hl] acc (2) direct addressing mode: direct addressing mode indicates the ram address by immediate data. for example: lda x ; acc ram[x] sta x ; ram[x] acc (3) zero-page addressing mode for zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. for example: std #k,y ; ram[y] #k add #k,y; ram[y] ram[y] + #k program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter ( pc ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program rom. for a 3k - byte size rom, pc can indicate address form 000h - bffh, for branch and call instrcutions, pc is changed by instruction indicating. (1) branch instruction: (1) branch instruction: (1) branch instruction: (1) branch instruction: (1) branch instruction: sbr a sbr a sbr a sbr a sbr a object code: 00aa aaaa condition: sf=1; pc pc 11-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc pc +1( branch condition not satisified) pc original pc value + 1 lbr a lbr a lbr a lbr a lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc a ( branch condition satisified) pcaaaaaaaaaaaa
7 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product sf=0 ; pc pc + 2 ( branch condition not satisified ) pc original pc value + 2 (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: scall a scall a scall a scall a scall a object code: 1110 nnnn condition : pc a ; a=8n+6 ; n=1..15 ; a=86h, n=0 lcall a lcall a lcall a lcall a lcall a object code: 0100 0aaa aaaa aaaa condition: pc a pc0aaaaaaaaaaa ret ret ret ret ret object code: 0100 1111 condition: pc stack[sp]; sp + 1 pc the return address stored in stack rt i rt i rt i rt i rt i object code: 0100 1101 condition : flag. pc stack[sp]; ei 1; sp + 1 pc the return address stored in stack (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc,the interrupt vectors are as following: int0 int0 int0 int0 int0 (external interrupt from p0.2) pc000000000010 trga trga trga trga trga (timer a overflow interrupt) pc000000000110 trgb trgb trgb trgb trgb (time b overflow interrupt) pc000000001000 tbi tbi tbi tbi tbi (time base interrupt) pc000000001010 pc 0 0 0 0 a a a a a a a a
8 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product int1 int1 int1 int1 int1 (external interrupt from p0.0) pc000000001100 (4) reset operation: (4) reset operation: (4) reset operation: (4) reset operation: (4) reset operation: pc000000000000 (5) other operations: (5) other operations: (5) other operations: (5) other operations: (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 there are four kinds of flag, cf ( carry flag ), zf ( zero flag ), sf ( status flag ) and gf ( general flag ), these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation . all flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after rti instruction executed . (1) carry flag ( cf ) the carry flag is affected by following operation: a. addition : cf as a carry out indicator, when the addition operation has a carry-out, cf will be "1", in another word, if the operation has no carry-out, cf will be "0". b. subtraction : cf as a borrow-in indicator, when the subtraction operation must has a borrow, in the cf will be "0", in another word, if no borrow-in, cf will be "1". c. comparision: cf is as a borrow-in indicator for comparision operation as the same as subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : for tfcfc instruction, the content of cf sends into sf then clear itself "0". for ttsfc instruction, the content of cf sends into sf then set itself "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generate a "0" result, the zf will be "1", otherwise, the zf will be "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status . accumulator accumulator accumulator accumulator accumulator accumulator is a 4-bit data register for temporary data . for the arithematic, logic and comparative opertion .., acc plays a role which holds the source data and result . flags flags flags flags flags
9 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product alu alu alu alu alu the arithematic operation of 4 - bit data is performed in alu unit . there are 2 flags can be affected by the result of alu operation, zf and sf . the operation of alu can be affected by cf only . alu structure alu structure alu structure alu structure alu structure alu supported user arithematic operation function, including : addition, subtraction and rotaion. alu function alu function alu function alu function alu function (1) addition: for instruction addam, adcam, addm #k, add #k,y .... alu supports addition function. the addition operation can affect cf and zf. for addition operation, if the result is "0", zf will be "1", otherwise, not equal "0", zf will be "0", when the addition operation has a carry-out. cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: for instruction subm #k, suba #k, sbcam, decm... alu supports user subtraction function . the subtraction operation can affect cf and zf, for subtraction operation, if the result is negative, cf will gf is a one bit general purpose register which can be set, clear, test by instruction sgf, cgf and tgs. program example: check following arithematic operation for cf, zf, sf cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0 a. sf is initiated to "1" for reset condition . b. branch instruction is decided by sf, when sf=1, branch condition will be satisified, otherwise, branch condition will not be satisified by sf = 0 . (4) general flag ( gf ) zf cf sf gf alu data bus
10 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb (3) rotation: there are two kinds of rotation operation, one is rotation left, the other is rotation right. rlca instruction rotates acc value to left, shift the cf value into the lsb bit of acc and the shift out data will be hold in cf. rrca instruction operation rotates acc value to right, shift the cf value into the msb bit of acc and the shift out data will be hold in cf. program example: to rotate acc right and shift a "1" into the msb bit of acc . ttcfs; cf 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register hl register hl register hl register hl register are two 4-bit registers, they are used as a pair of pointer for the address of ram memory and also 2 independent temporary 4-bit data registers. for some instruction, l register can be a pointer to indicate the pin number ( port4, port6, port7 ) . hl register structure hl register structure hl register structure hl register structure hl register structure hl register function hl register function hl register function hl register function hl register function (1) for instruction : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah, hl register used as a temporary register . program example: load immediate data "5h" into l register, "dh" into h register. ldl #05h; ldh #0dh; (2) for instruction ldam, stam, stami .., hl register used as a pointer for the address of ram memory. example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 be "0", it means a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf will be "1", otherwise, zf will be "1".
11 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product program example: store immediate data #ah into ram of address 35h. ldl #5h; ldh #3h; stdmi #0ah; ram[35] ah (3) for instruction : selp, clpl, tfpl, l regieter be a pointer to indicate the bit of i/o port. when lr = 0 - 1, indicate p4.0 - p4.1. program example: to set bit 1 of port4 to "1" ldl #01h; sepl ; p4.1 1 stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer is a 4-bit register which stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition . when a new subroutine is accepted, the sp will be decreased one automatically, in another word, if returning from a subroutine, the sp will be increased one . the data transfer between acc and sp is by instruction of "ldasp" and "stasp". data pointer (dp) data pointer (dp) data pointer (dp) data pointer (dp) data pointer (dp) data pointer is a 12-bit register which stores the address of rom can indicate the rom code data specified by user (refer to data rom). clock and timing generator clock and timing generator clock and timing generator clock and timing generator clock and timing generator the clock generator is supported by a single clock system, the clock source comes from crystal (resonator) or rc oscillation, the working frequency range is 32 khz to 100 khz depending on the working voltage. clock and timing generator structure clock and timing generator structure clock and timing generator structure clock and timing generator structure clock and timing generator structure the clock generator connects outside compoments ( crystal or resonator by xin and xout pin for crystal osc type, capacitor for rc osc type, these two type is decided by mask option) the clock generator generates a basic system clock "fc". when cpu sleeping, the clock generator will be stoped until the sleep condition released. the system clock control generates 4 basic phase signals ( s1, s2, s3, s4 ) and system clock . sleep xin/clk xout clock generator system clock control fc system clock s1 s2 s3 s4 mask option mask option for choose crystal or rc oscillation xin
12 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product clock and timing generator function clock and timing generator function clock and timing generator function clock and timing generator function clock and timing generator function the frequency of fc is the oscillation frequency for xin, xout by crystal ( resonator) or by rc osc. when cpu sleeps, the xout pin will be in "high" state . the instruction cycle equal 4 basic clock fc. 1 instructure cycle = 4 / fc timing generator and time base timing generator and time base timing generator and time base timing generator and time base timing generator and time base the timing generator produces the system clock from basic clock pulse which can be normal mode or slow mode clock. 1 instruction cycle = 4 basic clock pulses there are 22 stages time base . when working in the single clock mode, the timebase clock source is come from fc. time base provides basic frequency for following function: 1. tbi (time base interrupt) . 2. timer/counter, internal clock source. 3. warm-up time for sleep - mode releasing. time base interrupt (tbi ) time base interrupt (tbi ) time base interrupt (tbi ) time base interrupt (tbi ) time base interrupt (tbi ) the time base can be used to generate a fixed frequency interrupt . there are 8 kinds of frequencies can be selected by setting "p25" single clock mode p25 3 2 1 0 ( initial value 0000 ) 0 0 x x: interrupt disable 0 1 0 0: interrupt frequency xin / 2 9 hz 0 1 0 1: interrupt frequency xin / 2 10 hz 0 1 1 0: interrupt frequency xin / 2 12 hz 0 1 1 1: interrupt frequency xin / 2 13 hz 1 1 0 0: interrupt frequency xin / 2 14 hz 1 1 0 1: interrupt frequency xin / 2 15 hz 1 1 1 0: interrupt frequency xin / 2 16 hz 1 1 1 1: interrupt frequency xin / 2 17 hz 1 0 x x: reserved fc prescaler binary counter 12 3 0 5 6 7 8 9 10 11 12 13 421 20 19 18 17 16 15 14 xin xout crystal connection xin xout resistor connection
13 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product interrupt control trga request timer control i nternal clock p28 12 bit counter tmsa ipsa data bus timer control internal clock p29 12 bit counter tmsb ipsb trgb request port 28 3 2 1 0 tmsa ipsa initial state: 0000 timer/counter mode selection tmsa (b) function description 0 0 stop 0 1 reserved 1 0 timer mode 1 1 reserved port 29 3 2 1 0 tmsb ipsb initial state: 0000 internal pulse-rate selection ipsa(b) function description 0 0 xin/2 hz 0 1 xin/2 hz 1 0 xin/2 hz 1 1 xin/2 hz 5 7 11 15 timer/counter control timer/counter control timer/counter control timer/counter control timer/counter control timer/counter command port: p28 is the command port for timer/countera and p29 is for the timer/ counterb. timer / counter ( timera, timerb) timer / counter ( timera, timerb) timer / counter ( timera, timerb) timer / counter ( timera, timerb) timer / counter ( timera, timerb) em73361a only can support timer function for timera and timerb independently. for timera, the counter data is saved in timer register tah, tam, tal, which user can set counter initial value and read the counter value by instruction "ldatah(m,l), statah(m,l)" and timerb register is tbh, tbm, tbl and w/r instruction "ldatbh (m,l), statbh (m,l)". the basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, p28 and p29 are the command ports for timera and timer b, user can choose different internal clock rate by setting these two ports. when timer/counter overflow, it will generate a trga(b) interrupt request to interrupt control unit.
14 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product timer/counter function timer/counter function timer/counter function timer/counter function timer/counter function each timer/counter can execute the timer function independly. timer mode for timer mode ,timer/counter increase one at any rising edge of internal pulse . user can choose 4 kinds of internal pulse rate by setting ipsb for timerb (ipsa for timera). when timer/counter counts overflow, trgb (trga) will be generated to interrupt control unit. program example: to generate trga interrupt request after 60 ms with system clock xln=32k hz ldia #0100b; exae; enable mask 2 eicil 110111b; internupt latch 0, enable ei ldia #04h; ldia #0ch; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: xin/2 5 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: xin/2 5 ; xin = 32khz the time of timer counter count one = 2 5 /xin = 32/32k=1ms the number of internal pulse to get timer overflow = 60 ms/ 1ms = 60 = 03ch the preset value of timer/counter register = 1000h - 03ch = 0fc4h interrupt function interrupt function interrupt function interrupt function interrupt function there are 3 internal interrupt sources and 2 external interrupt sources. multiple interrupts are admitted according the priority . type type type type type interrupt source interrupt source interrupt source interrupt source interrupt source priority priority priority priority priority interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt program rom program rom program rom program rom program rom latch latch latch latch latch enable condition enable condition enable condition enable condition enable condition entry address entry address entry address entry address entry address external external interrupt (int0) 1 il5 ei=1 002h internal reserved 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt (int1) 6 il0 ei=1,mask0=1 00ch statal; internal pulse timerb (timera )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7
15 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product interrupt structure interrupt structure interrupt structure interrupt structure interrupt structure interrupt controller: il0-il5 : interrupt latch . hold all interrupt requests from all interrupt sources. ilr can not be set by program, but can be reset by program or system reset, so il only can decide which interrupt source can be accepted. mask0-mask3 : mask register can promit or inhibit all interrupt sources. ei : enable interrupt flip-flop can promit or inhibit all interrupt sources, when inter- rupt happened, ei is cleared to "0" automatically, after rti instruction happened, ei will be set to "1" again . priority checker: check interrupt priority when multiple interrupts happened. interrupt function interrupt function interrupt function interrupt function interrupt function the procedure of interrupt operation: 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts happened. 5. clear the il for which interrupt source has already be accepted. 6. to excute interrupt subroutine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack . set ei to accept other interrupt requests. program example: to enable interrupt of "trga" ldia #1100b; exae; set mask register "1100b" eicil 111111b ; enable interrupt f.f. int1 reset by system reset and program i nstruction mask0 mask1 mask1 mask2 mask3 il0 reserved reserved r0 il1 tbi r1 il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb int1
16 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product power saving function ( sleep / hold function ) power saving function ( sleep / hold function ) power saving function ( sleep / hold function ) power saving function ( sleep / hold function ) power saving function ( sleep / hold function ) during sleep and hold condition, cpu holds the system's internal status with a low power consumption, for the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for the stability of system clock running after wakeup . in the other way, for the hold mode, the system clock does not stop at all and it does not need a warm-up time any way. the sleep and hold mode is controlled by port 16 and released by p0(0..3)/wakeup0..3. sleep and hold condition: 1. osc stop ( sleep only ) and cpu internal status held . 2. internal time base clear to "0". 3. cpu internal memory ,flags, register, i/o held original states. 4. program counter hold the executed address after sleep release. release condition: 1. osc start to oscillating.(sleep only). 2. warm-up time passing ( sleep only ). 3. according pc to execute the following program. there is one kind of sleep/hold release mode . 1. edge release mode: release sleep/hold condition by the falling edge of any one of p0(0..3)/wakeup0..3. note : there are 4 independent mask options for wakeup function in em73360. so, the wakeup function of p0(0..3)/wakeup0..3 are enabled or disabled inpendently. lcd driver lcd driver lcd driver lcd driver lcd driver em73361a can directly drive the liquid crystal display (lcd) and has 27 segment, 3 common output pins. there are total 27 x 3 dots can be display. the vdd, vee and vss pins are the bias voltage inputs of the lcd driver. the va and vb are used to the voltage double for 3v system. the method of lcd programming is i/o mapping. control of lcd driver control of lcd driver control of lcd driver control of lcd driver control of lcd driver the lcd driver control command register is p27. when ldc is 00, the lcd is disabled. when ldc is 01, the lcd is blanking, p16 3 2 1 0 initial value :0000 swwt set wake-up warm-up time 2 /xin 2 /xin 2 /xin hold mode se enable sleep/hold 0 reserved 1 enable sleep / hold rnode 0 1 wake-up in edge release mode reserved 0 0 0 1 1 0 1 1 17 13 15 wm se swwt wm set wake-up release mode
17 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product the com pins are inactive and the seg pins continously output the display data. when ldc is 11, the lcd driver enables, the power swich is turned on and it cannot be turned off forever except the cpu is reseted or sleeping. users must enable the lcd driver by self when the cpu is waked up. port27 3 2 1 0 initial value : 0000 ldc duty ldc lcd display control duty driving method select 0 0 lcd display disable & change duty 0 0 reserved 0 1 blanking 0 1 1/3 duty (1/2 bias) 1 0 reserved 1 0 1/2 duty (1/2 bias) 1 1 lcd display enable 1 1 static lcd driving methods there are four kinds of driving methods can be selected by duty (p27.0~p27.1). the driving waveforms of lcd driver are as below : c o m 2 c o m 1 c o m 0 seg0 seg1 seg2 : com0 com1 com2 seg0 seg0-com0 on seg0-com1 off frame frame frame on off 1/3 duty (1/2 bias) 1/2duty (1/2 bias) static driving method bit3 bit2 bit1 bit0 1/3 duty - com2 com1 com0 1/2 duty - - com1 com0 static - - - com0 lcd drive voltage em73361a provides 2 kinds of lcd bias methods, capacitor divider and resistor divider, when the lcd bias method is capacitor divider,the va is connected a capacitor to vb and the vee is connected a capacitor to vss. the output of vee is 1.5v for lcd bias voltage. when the lcd bias method is resistor divider, the va, vb and vee are floating. lcd frame frequency : according to the drive method to set the frame frequency. driving method frame frequency (hz) 1/3 duty 43 x (3/3) = 43 1/2 duty 43 x (3/2) = 64 static 43 the relation between lcd display data and driving method
18 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product lcd display operation lcd display operation lcd display operation lcd display operation lcd display operation the lcd programming method is i/o mapping and p10~p12 are must be used. address register of lcd display buffer it is a 5-bit register to specify address for lcd display buffer. port11 port10 3 2 1 0 3 2 1 0 initial value :0000 0000 a4 a3 a2 a1 a0 data register of lcd display buffer p12 is a 3-bit data register to read or write lcd display buffer. port12 3 2 1 0 initial value : 0000 d2 d1 d0 tone generator tone generator tone generator tone generator tone generator em73361a has a built-in tone generator. it is a binary down counter. when the cpu is reseted or sleeping, the tone generator is disabled and the output (p4.0/tone) is high. xin tone generator p23, p24 output control p30.0 tone tone fo high tone generator command register port30 3 2 1 0 * * * sm initial value : 0000 sm sound generator mode 0 tone generator disable 1 tone generator enable va vb v ee v dd v ss 1.5v 0.1f 3v va vb v ee v dd v ss 3v resistor divider capacitor divider
19 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product tone frequency register the 8-bit tone frequency register is p24 and p23. the tone frequency will be changed when user output the different data to p23. thus, the data must be output to p24 before p23 when user want to change the 8-bit tone frequency (tf). port24 port23 3 2 1 0 3 2 1 0 initial value : 1111 1111 higher nibble register lower nibble register ** f1=xin/(tf+1), tf=1~255, tf 0 ** example : xin=32k hz, tf=00110001b. ? fo=32k hz/50=655.36 hz watch-dog-timer (mask option) watch-dog-timer (mask option) watch-dog-timer (mask option) watch-dog-timer (mask option) watch-dog-timer (mask option) watch-dog-timer can help user to detect the malfunction (runaway) of cpu and give system a time up signal every certain time . user can use the time up signal to give system a reset signal when system is fail. when cpu is reseted or sleeping, the watch-dog-timer is disabled. users must enable the watch-dog-timer by self when cpu is waked up. the basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit . the wdt counter counts for a certain time to check the cpu status, if there is no malfunction happened, the counter will be cleared and counting . otherwise, if there is a malfunction happened, the wdt control will send a wdt signal ( low active ) to outside, user can use this signal to reset cpu . the wdt checking period is assign by p21 ( wdt command port ) p21 is the control port of watchdog timer, and the watchdog timer timeup signal is output by p4.1/wdt, user can use this timeup signal (active low) to reset cpu and initialize system. port 21 3 2 1 0 initial value :0000 cwc * * wdt cwc clear watchdog timer counter 0 clear counter then return to 1 1 nothing wdt set watchdog timer detect time 0 3 x 2 13 /fc=3 x 2 13 /32 khz=0.75 sec 1 7 x 2 13 /fc=7 x 2 13 /32k hz=1.75 sec p4.1 output data latch p4.1 0 1 2 3 c ounter clear request wdt control system reset p4.1 output data wdt command port p21 wdt counter fc/2 r s q f/f 13
20 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product program example to enable wdt with 3 x 2 13 /fc detection ftime. ldia #0000b outa p21; set wdt detection time and clear wdt counter resetting function resetting function resetting function resetting function resetting function when cpu in normal working condition and reset pin holds in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, and when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : hardware condition in reset state initial value program counter 000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p10, 11, 12, 16, 21, 25, 27, 28, 29, 30 00h p4, 5, 6, 7, 23, 24 0fh xin start oscillation the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset
21 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product em73361a i/o port description : em73361a i/o port description : em73361a i/o port description : em73361a i/o port description : em73361a i/o port description : port port port port port input function input function input function input function input function output function output function output function output function output function note note note note note 0 e input port , wakeup function 1-- -- 2-- -- 3-- -- 4 e input port e output port, p4.0/tone,p4.1/wdt, p4(2..3) /seg(26..25) 5 e input port e p5(0..3)/seg(24..21) 6 e input port e p6(0..3)/seg(20..17) 7 e input port e p7(0..3)/seg(16..13) 8-- -- 9-- -- 10 -- i address register of lcd display buffer low nibble 11 -- i address register of lcd display buffer high nibble 12 -- i data register of lcd display buffer 13 -- -- 14 -- -- 15 -- -- 16 i sleep/hold mode control register 17 -- 18 -- 19 -- 20 -- 21 i watch-dog-timer control register 22 -- 23 i sound effect frequency register low nibble 24 i sound effect frequency register high nibble 25 i timebase control register 26 -- 27 i lcd control register 28 i timer/counter a control register 29 i timer/counter b control register 30 i sound effect command register 31 --
22 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings items items items items items sym. sym. sym. sym. sym. ratings ratings ratings ratings ratings conditions conditions conditions conditions conditions supply voltage v dd -0.5v to 6v input voltage v in -0.5v to v dd +0.5v output voltage v o -0.5v to v dd +0.5v power dissipation p d 200mw t opr =50 o c operating temperature t opr 0 o c to 50 o c storage temperature t stg -55 o c to 125 o c recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions items items items items items sym. sym. sym. sym. sym. ratings ratings ratings ratings ratings conditions conditions conditions conditions conditions supply voltage v dd 2.2v to 3.6v fc=32khz input voltage v ih 0.9xv dd to v dd v il 0v to 0.10xv dd
23 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics (v dd =3.00.3v, v ss =0v, t opr =25 o c) parameters parameters parameters parameters parameters sym. sym. sym. sym. sym. min. min. min. min. min. typ. typ. typ. typ. typ. max. max. max. max. max. unit unit unit unit unit conditions conditions conditions conditions conditions supply current i dd -1020av dd =3.3v, cap. divider, no load, no lvr, fc=32khz -3060av dd =3.3v, res. divider, no load, no lvr, fc=32khz -5085av dd =3.3v, no load, with lvr, fc=32khz -58av dd =3.3v, hold mode, no lvr - 0.1 1 a v dd =3.3v, sleep mode, no lvr hysteresis voltage v hys+ 0.50v dd - 0.75v dd v reset, p0 v hys- 0.20v dd - 0.40v dd v input current i ih - 20 30 a port0, pull-down, v ih =v dd -30 -20 - a port0, pull-up, v ih =v ss - - 1 a port0, none i il - -320 -500 a push-pull , v dd =3.3v, v il =0.4v, except p4.0, tone output voltage v oh 2.4 - - v push-pull, p4.0(high current pmos), tone, v dd =2.7v,i oh =-1ma 2.0 - - v push-pull, p4.0(low current pmos), v dd =2.7v, i oh =-60a v ol - - 0.3 v v dd =2.7v, i ol =1ma leakage current i lo - - 1 a open-drain.v dd =3.3v, v o =3.3v input resistor r in 30 70 110 k ? reset lcd bias voltage v ee 1 / 2 v dd -0.1 1 / 2 v dd 1 / 2 v dd +0.1 v voltage halfer com, seg pins v 01 v dd -0.1 v dd - vi 01 =-5a, cap. divider output current v 02 v ee -0.1 v ee v ee +0.1 vi 02 =5a, cap. divider v 03 -v ss v ss +0.1 vi 03 =5a, cap. divider frequency stability - 20 - % fc=32khz, rc osc, r=750k ? , [f(3.0v)-f(2.7v)]/f(3.0v) frequency variation - 20 - % fc=32khz, v dd =3.0v,rc osc, r=750k ? , [f(typical)-f(worse case)]/f(typical) lvr reset voltage v lvr - 1.5 - v lvr reset release v rlvr - 1.8 - v voltage
24 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product reset pin type reset pin type reset pin type reset pin type reset pin type type reset-a reset mask option xin xout crystal osc. xin xout rc osc. (inverter) : mask option wakeup function mask option : mask option input data special function control input wakeup function mask option input pin type input pin type input pin type input pin type input pin type type input-h type input-j oscillation pin type oscillation pin type oscillation pin type oscillation pin type oscillation pin type type osc-a type osc-f
25 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product i/o pin type i/o pin type i/o pin type i/o pin type i/o pin type type i/o type i/o-d input data output data path b mux path a type i/o output data latch mask option : mask option : mask option output data latch type i/o input data output data special function output path b path a : mask option output data latch type i/o input data output data special function output path b path a special function control output type i/o-n type i/o-o path a : for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b : for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high. type i/o-p
26 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product application circuit application circuit application circuit application circuit application circuit p0.0 p0.1 p0.2 tone p4.0/tone reset vss va vb vee xout xin 20p 32.768khz x'tal osc type 0.1f 0.1f seg0~ seg12 com0~ com2 lcd pannel v bat v bat v dd em73361a buzzer reset 3v 20p xout xin rc osc type capacitor driver vee resistor driver 0.1f
27 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product padno. padno. padno. padno. padno. symbol symbol symbol symbol symbol x x x x x y y y y y 1 seg2 -685.5 583.8 2 seg1 -685.5 473.3 3 seg0 -685.5 362.9 4 com1 -685.5 252.4 5 com0 -685.5 141.9 6 vee -685.5 31.5 7 vb -685.5 -79.0 8 va -685.5 -189.4 9 xin -685.5 -299.9 10 xout -685.5 -639.3 11 vss -522.3 -785.5 12 vdd -409.3 -785.5 13 reset -296.3 -785.5 14 p0.0 -185.9 -785.5 15 p0.1 -71.9 -785.5 16 p0.2 38.6 -785.5 17 p0.3 152.6 -785.5 pad diagram pad diagram pad diagram pad diagram pad diagram chip size : 1710 m x 1910 m 40 42 44 43 45 46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 35 36 38 39 seg8 seg7 seg6 seg5 seg4 seg3 p7.2 p7.1 p7.3 seg12 seg11 seg10 seg9 p0.1 p0.0 reset v dd v ss xin p4.1 p4.0 tone p0.3 p0.2 p7.0 p6.2 p6.1 p6.0 p5.3 p5.2 p5.1 p4.3 p5.0 p4.2 p6.3 com2 seg2 seg1 seg0 com1 com0 v ee vb va (0,0) y x em73361a 41 test xout elan
28 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product padno. padno. padno. padno. padno. symbol symbol symbol symbol symbol x x x x x y y y y y 18 tone 263.0 -785.5 19 p4.0 373.5 -785.5 20 p4.1 483.9 -785.5 21 test 685.5 -741.7 22 com2 685.5 -631.3 23 p4.2 685.5 -520.8 24 p4.3 685.5 -410.4 25 p5.0 685.5 -299.9 26 p5.1 685.5 -189.4 27 p5.2 685.5 -79.0 28 p5.3 685.5 31.5 29 p6.0 685.5 141.9 30 p6.1 685.5 252.4 31 p6.2 685.5 362.9 32 p6.3 685.5 473.3 33 p7.0 685.5 583.8 34 p7.1 662.4 785.4 35 p7.2 552.0 785.4 36 p7.3 441.5 785.4 37 seg12 331.1 785.4 38 seg11 220.6 785.4 39 seg10 110.1 785.4 40 seg9 -0.3 785.4 41 seg8 -110.8 785.4 42 seg7 -221.2 785.4 43 seg6 -331.7 785.4 44 seg5 -442.2 785.4 45 seg4 -552.6 785.4 46 seg3 -663.1 785.4 note : for pcb llayout, ic substrate must be floated or connect to v ss .
29 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product instruction table instruction table instruction table instruction table instruction table (1) data transfer (1) data transfer (1) data transfer (1) data transfer (1) data transfer mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s lda x 0110 1010 xxxx xxxx acc ram[x] 2 2 - z 1 ldam 0101 1010 acc ram[hl] 1 1 - z 1 ldax 0110 0101 acc rom[dp] l 12-z1 ldaxi 0110 0111 acc rom[dp] h ,dp+1 1 2 - z 1 ldh #k 1001 kkkk hr k11--1 ldhl x 0100 1110 xxxx xx00 lr ram[x],hr ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc k11-z1 ldl #k 1000 kkkk lr k11--1 sta x 0110 1001 xxxx xxxx ram[x] acc 2 2 - - 1 stam 0101 1001 ram[hl] acc 1 1 - - 1 stamd 0111 1101 ram[hl] acc, lr-1 1 1 - z c stami 0111 1111 ram[hl] acc, lr+1 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] k22--1 stdmi #k 1010 kkkk ram[hl] k, lr+1 1 1 - z c' tha 0111 0110 acc hr 1 1 - z 1 tla 0111 0100 acc lr 1 1 - z 1 (2) rotate (2) rotate (2) rotate (2) rotate (2) rotate mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s rlca 0101 0000 cf acc 11czc' rrca 0101 0001 cf acc 11czc' ( 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s adcam 0111 0000 acc acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc acc+k 2 2 - z c' addam 0111 0001 acc acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ram[hl] +k 2 2 - z c' deca 0101 1100 acc acc-1 1 1 - z c decl 0111 1100 lr lr-1 1 1 - z c decm 0101 1101 ram[hl] ram[hl]-1 1 1 - z c inca 0101 1110 acc acc + 1 1 1 - z c'
30 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product incl 0111 1110 lr lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc k-acc 2 2 - z c sbcam 0111 0010 acc ram[hll - acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] k - ram[hl] 2 2 - z c ( ( ( ( ( 4) logical operation 4) logical operation 4) logical operation 4) logical operation 4) logical operation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s anda #k 0110 1110 0110 kkkk acc acc&k 2 2 - z z' andam 0111 1011 acc acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc acc k 2 2 - z z' oram 0111 1000 acc acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ram[hl] k 2 2 - z z' xoram 0111 1001 acc acc^ram[hl] 1 1 - z z' (5) exchange (5) exchange (5) exchange (5) exchange (5) exchange mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch (6) branch (6) branch (6) branch (6) branch mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s sbr a 00aa aaaa if sf=1 then pc pc 11-6 .a 5-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc a else null 2 2 - - 1 (7) compare (7) compare (7) compare (7) compare (7) compare mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c - - - - - -
31 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product (8) bit manipulation (8) bit manipulation (8) bit manipulation (8) bit manipulation (8) bit manipulation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s clm b 1111 00bb ram[hl] b 011--1 clp p,b 0110 1101 11bb pppp port[p] b 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b 022--1 sem b 1111 01bb ram[hl] b 111--1 sep p,b 0110 1101 01bb pppp port[p] b 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b 122--1 tf y,b 0110 1100 00bb yyyy sf ram[y] b '22--* tfa b 1111 10bb sf acc b '11--* tfm b 1111 11bb sf ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf port[p] b '22--* tfpl 0110 0001 sf port[lr 3-2 +4] lr 1-0 '12--* tt y,b 0110 1100 10bb yyyy sf ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf port[p] b 22--* (9) subroutine (9) subroutine (9) subroutine (9) subroutine (9) subroutine mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s lcall a 0100 0aaa aaaa aaaa stack[sp] pc, 2 2 - - - sp sp -1, pc a scall a 1110 nnnn stack[sp] pc, 1 2 - - - sp sp - 1, pc a,a = 8n + 6 (n =115 ),0086h (n = 0) ret 0100 1111 sp sp + 1, pc stack[sp] 1 2 - - - (10) input/output (10) input/output (10) input/output (10) input/output (10) input/output mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s ina p 0110 1111 0100 pppp acc port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] k22--1 outa p 0110 1111 000p pppp port[p] acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ram[hl] 2 2 - - 1 (11) flag manipulation (11) flag manipulation (11) flag manipulation (11) flag manipulation (11) flag manipulation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cgf 0101 0111 gf 011--1 sgf 0101 0101 gf 111--1
32 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product tfcfc 0101 0011 sf cf', cf 0110-* tgs 0101 0100 sf gf 1 1 - - * ttcfs 0101 0010 sf cf, cf 1111-* tzs 0101 1011 sf zf 1 1 - - * (12) interrupt control (12) interrupt control (12) interrupt control (12) interrupt control (12) interrupt control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cil r 0110 0011 11rr rrrr il il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif 0,il il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif 1,il il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp sp+1,flag.pc 1 2 * * * stack[sp],eif 1 (13) cpu control (13) cpu control (13) cpu control (13) cpu control (13) cpu control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s ldadpl 0110 1010 1111 1100 acc [dp] l 22-z1 ldadpm 0110 1010 1111 1101 acc [dp] m 22-z1 ldadph 0110 1010 1111 1110 acc [dp] h 22-z1 ldasp 0110 1010 1111 1111 acc sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc [ta] l 22-z1 ldatam 0110 1010 1111 0101 acc [ta] m 22-z1 ldatah 0110 1010 1111 0110 acc [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc [tb] l 22-z1 ldatbm 0110 1010 1111 1001 acc [tb] m 22-z1 ldatbh 0110 1010 1111 1010 acc [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h acc 2 2 - - 1
33 * this specification are subject to be changed without notice. 10.8.2001 em73361a em73361a em73361a em73361a em73361a 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product **** symbol description **** symbol description **** symbol description **** symbol description **** symbol description symbol symbol symbol symbol symbol description description description description description symbol symbol symbol symbol symbol description description description description description hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag gf general flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ? timer/counter a ? timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a (timer/counter b) register [ta] m ([tb] m ) middle 4-bit of timer/counter a [ta] h ([tb] h ) high 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register transfer ? exchange + addition - substraction & logic and logic or ^ logic xor ' inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch pc 11-6 bit 11 to 6 of program counter lr 1 -0 contents of bit assigned by bit a 5-0 bit 5 to 0 of destination address for 1 to 0 of lr branch instruction lr 3-2 bit 3 to 2 of lr - -

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